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NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) 512MB, 256MB and 128MB PC3200, PC2700 and PC2100 Unbuffered DDR DIMM 184 pin Unbuffered DDR DIMM
Based on DDR400/333/266 256M bit B Die device
Features
* 184 Dual In-Line Memory Module (DIMM) * Unbuffered DDR DIMM based on 256M bit die B device, organized as either 32Mbx8 or 16Mbx16 * Performance: PC3200 PC2700 PC2100 Speed Sort DIMM CAS Latency fCK tCK Clock Frequency Clock Cycle 5T 3 200 5 400 6K 2.5 166 6 333 75B 2.5 133 7.5 266 MHz ns MHz Unit * DRAM DLL aligns DQ and DQS transitions with clock transitions * Address and control signals are fully synchronous to positive clock edge * Programmable Operation: - DIMM CAS Latency: 2, 2.5, 3 - Burst Type: Sequential or Interleave - Burst Length: 2, 4, 8 - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes * Automatic and controlled precharge commands * 7.8 s Max. Average Periodic Refresh Interval * Serial Presence Detect EEPROM * Gold contacts * SDRAMs are packaged in TSOP packages * "Green" packaging - lead free
fDQ DQ Burst Frequency
* Intended for 133, 166 and 200 MHz applications * Inputs and outputs are SSTL-2 compatible * VDD = VDDQ = 2.5V 0.2V (2.6V 0.1V for PC3200) * SDRAMs have 4 internal banks for concurrent operation * Differential clock inputs * Data is read or written on both clock edges
Description
NT512D64S8HB0G, NT512D64S8HB1G, NT512D64S8HB1GY, NT512D72S8PB0G, NT256D64SH88B0G, NT256D64SH88B1G, NT256D64SH88B1GY, NT256D72S89B0G and NT128D64SH4B1G are unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Modules (DIMM). NT512D64S8HB1GY and NT256D64SH88B1GY are packaged using lead free technology.
NT512D64S8HB0G, NT512D64S8HB1G and NT512D64S8HB1GY are 512MB modules organized as dual ranks using sixteen 32Mx8 TSOP devices. NT512D72S8PB0G has ECC and is organized as dual ranks using eighteen 32Mx8 TSOP devices. NT256D64SH88B0G, NT256D64SH88B1G and NT256D64SH88B1GY are 256MB modules organized as single rank using eight 32Mx8 TSOP devices. NT256D72S89B0G has ECC and is organized as single rank using nine 32Mx8 TSOP devices. NT128D64SH4B1G are 128MB modules, organized as single rank using four 16Mx16 TSOP devices.
Depending on the speed grade, these DIMMs are intended for use in applications operating up to 200 MHz clock speeds and achieves high-speed data transfer rates of up to 400 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) can be accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC.
REV 2.2
Aug 3, 2004
1
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM Ordering Information
Part Number NT512D72S8PB0G-5T Organization Speed Power Leads
64Mx72
NT512D64S8HB1G-5T 64Mx64 NT512D64S8HB1GY-5T (lead free) NT256D72S890G-5T PC3200 200MHz (5ns @ CL = 3) 32Mx72 DDR400 3-3-3 166MHz (6ns @ CL = 2.5) 2.6V
NT256D64S88B1G-5T 32Mx64 NT256D64S88B1GY-5T (lead free) NT128D64SH4B1G-5T 16Mx64
NT512D64S8HB1G-6K 64Mx64 NT512D64S8HB1GY-6K (lead free) NT256D64S88B1GY-6K (lead free) 32Mx64 NT256D64S88B0G-6K 2.5V NT128D64SH4B1G-6K 16Mx64 PC2700 166MHz (6ns @ CL = 2.5) DDR333 2.5-3-3 133MHz (7.5ns @ CL = 2)
Gold
NT512D64S8HB0G-75B
64Mx64 PC2100 133MHz (7.5ns @ CL = 2.5) 32Mx64 DDR266B 2.5-3-3 100MHz (10ns @ CL = 2)
NT256D64S88B0G-75B
NT128D64SH4B1G-75B
16Mx64
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Nanya Technology Corporation
Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688
REV 2.2
Aug 3, 2004
2
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM Pin Description
CK0, CK1, CK2, CK0, CK1, CK2 CKE0, CKE1 RAS CAS WE S0, S1 A0-A9, A11, A12 A10/AP BA0, BA1 VREF VDDID Differential Clock Inputs. Clock Enable Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Auto-precharge SDRAM Bank Address Inputs Ref. Voltage for SSTL_2 inputs VDD Identification flag. DQ0-DQ63 DQS0-DQS7 DM0-DM7 VDD VDDQ VSS NC SCL SDA SA0-2 VDDSPD Data input/output Bidirectional data strobes Input Data Mask Power Supply voltage for DQs Ground No Connect Serial Presence Detect Clock Input Serial Presence Detect Data input/output Serial Presence Detect Address Inputs Serial EEPROM positive power supply
Pinout
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Front VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Back VSS DQ4 DQ5 VDDQ DM0/DQS9 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1/DQS10 VDD DQ14 DQ15 CKE1 VDDQ NC DQ20 A12 VSS DQ21 A11 DM2/DQS11 VDD DQ22 A8 DQ23 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 KEY 53 54 55 56 57 58 59 60 61 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 Front A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 NC NC VDD NC A0 NC VSS NC BA1 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 KEY 145 146 147 148 149 150 151 152 153 VSS DQ36 DQ37 VDD DM4/DQS13 DQ38 DQ39 VSS DQ44 Back VSS A6 DQ28 DQ29 VDDQ DM3/DQS12 A3 DQ30 VSS DQ31 NC NC VDDQ CK0 CK0 VSS NC A10 NC VDDQ NC Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Front VDDQ WE DQ41 CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS WP SDA SCL Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Back RAS DQ45 VDDQ S0 S1 DM5/DQS14 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 NC VDD DM6/DQS15 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7/DQS16 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
REV 2.2
Aug 3, 2004
3
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM Input/Output Functional Description
Symbol CK0, CK1, CK2, CK0, CK1, CK2 (SSTL) Type Polarity Cross point Active High Function The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR SDRAM command decoder when low and disables the S0, S1 (SSTL) Active Low Active Low command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is selected by S1. RAS, CAS, WE VREF VDDQ BA0, BA1 (SSTL) Supply Supply (SSTL) When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to be executed by the SDRAM. Reference voltage for SSTL-2 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when sampled at the rising clock edge. In addition to the column address, AP is used to A0 - A9 A10/AP A11, A12 (SSTL) invoke auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high, auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low, auto-precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. DQ0 - DQ63 DQS0 - DQS7, DQS9 - DQS16 CB0 - CB7 DM0 - DM8 VDD, VSS SA0 - SA2 SDA SCL VDDSPD Supply (SSTL) (SSTL) (SSTL) Input Supply Active High Active High Data and Check Bit input/output pins operate in the same manner as on conventional DRAMs. Data strobes: Output with read data, input with write data. Edge aligned with read data, centered on write data. Used to capture write data. Data Check Bit Input/Output pins. Used on ECC modules and is not used on x64 modules. The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. Power and ground for the DDR SDRAM input buffers and core logic Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pull-up. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. Serial EEPROM positive power supply.
CKE0, CKE1
(SSTL)
REV 2.2
Aug 3, 2004
4
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM Functional Block Diagram
2 Ranks, 16 devices, 32Mx8 DDR SDRAMs
S1 S0 DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7/DQS16 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6/DQS15 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5/DQS14 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQS4 DM4/DQS13 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS
D0
D8
D4
D12
D1
D9
D5
D13
D2
D10
D6
D14
D3
D11
D7
D15
BA0-BA1 A0-A13 RAS CAS CKE0 CKE1 WE Notes : 1. 2. 3. 4.
BA0-BA1 : SDRAMs D0-D15 A0-A13 : SDRAMs D0-D15 RAS : SDRAMs D0-D15 CAS : SDRAMs D0-D15 CKE : SDRAMs D0-D7 CKE : SDRAMs D8-D15 WE : SDRAMs D0-D15
VDDSPD VDD/VDDQ VREF VSS VDDID
SPD D0-D15 D0-D15 D0-D15 Strap: see Note 4 Serial PD
* Clock Wiring Clock Input SDRAMs *CK0/CK0 4 SDRAMs *CK1/CK1 6 SDRAMs *CK2/CK2 6 SDRAMs
* Wire per Clock Loading Table/ Wiring Diagrams
SCL WP
A0 SA0
A1 SA1
A2 SA2
SDA
DQ-to-I/O wiring is shown as recommended but may be changed. DQ/DQS/DM/CKE/S relationships must be maintained as shown. DQ, DQS, DM/DQS resistors: 22 Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ.
REV 2.2
Aug 3, 2004
5
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM Functional Block Diagram
1 Rank, 8 devices, 32Mx8 DDR SDRAMs
S0 DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS
DQS4 DM4/DQS13 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5/DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6/DQS15 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7/DQS16 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS
D0
D4
D1
D5
D2
D6
D3
D7
BA0-BA1 A0-A13 RAS CAS CKE0 WE
BA0-BA1 : SDRAMs D0-D7 A0-A13 : SDRAMs D0-D7 RAS : SDRAMs D0-D7 CAS : SDRAMs D0-D7 CKE : SDRAMs D0-D7 WE : SDRAMs D0-D7 Serial PD VDDSPD VDD/VDDQ VREF VSS VDDID SPD D0-D7 D0-D7 D0-D7 Strap: see Note 4 * Clock Wiring Clock Input SDRAMs *CK0/CK0 2 SDRAMs *CK1/CK1 3 SDRAMs *CK2/CK2 3 SDRAMs
* Wire per Clock Loading Table/ Wiring Diagrams
SCL WP
A0 SA0
A1 SA1
A2 SA2
SDA
Notes : 1. 2. 3. 4.
DQ-to-I/O wiring is shown as recommended but may be changed. DQ/DQS/DM/CKE/S relationships must be maintained as shown. DQ, DQS, DM/DQS resistors: 22 Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ.
REV 2.2
Aug 3, 2004
6
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM Functional Block Diagram
1 Rank, 4 devices, 16Mx16 DDR SDRAMs
S0 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQS LDM I/O 6 I/O 4 I/O 1 I/O 3 I/O 2 I/O 0 I/O 5 I/O 7 UDQS UDM I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9 D0 DQS4 DM4/DQS13 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 CS DQS5 DM5/DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 LDQS LDM I/O 6 I/O 4 I/O 1 I/O 3 I/O 2 I/O 0 I/O 5 I/O 7 UDQS UDM I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9 D2 CS
DQS3 DM3/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
LDQS LDM I/O 6 I/O 4 I/O 1 I/O 3 I/O 2 I/O 0 I/O 5 I/O 7 UDQS UDM I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9
CS DQS7 DM7/DQS16 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D1 DQS6 DM6/DQS15 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
LDQS LDM I/O 6 I/O 4 I/O 1 I/O 3 I/O 2 I/O 0 I/O 5 I/O 7 UDQS UDM I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9
CS
D3
BA0-BA1 A0-A13 RAS CAS CKE0 WE
BA0-BA1 : SDRAMs D0-D3 A0-A13 : SDRAMs D0-D3 RAS : SDRAMs D0-D3 CAS : SDRAMs D0-D3 CKE : SDRAMs D0-D3 WE : SDRAMs D0-D3 Serial PD VDDSPD VDD/VDDQ VREF VSS VDDID SPD D0-D3 D0-D3 D0-D3 Strap: see Note 4 * Clock Wiring Clock Input SDRAMs *CK0/CK0 NC *CK1/CK1 2 SDRAMs *CK2/CK2 2 SDRAMs
* Wire per Clock Loading Table/ Wiring Diagrams
SCL WP
A0 SA0
A1 SA1
A2 SA2
SDA
Notes : 1. 2. 3. 4.
DQ-to-I/O wiring is shown as recommended but may be changed. DQ/DQS/DM/CKE/S relationships must be maintained as shown. DQ, DQS, DM/DQS resistors: 22 Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ.
REV 2.2
Aug 3, 2004
7
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM Functional Block Diagram
2 Ranks, 18 devices (ECC), 32Mx8 DDR SDRAMs
S1 S0 DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DM8/DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7/DQS16 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6/DQS15 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5/DQS14 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQS4 DM4/DQS13 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS
D0
D9
D4
D13
D1
D10
D5
D14
D2
D11
D6
D15
D3
D12
D7
D16
VDDSPD VDD/VDDQ VREF VSS VDDID
SPD D0-D8 D0-D8 D0-D8 Strap: see Note 4
* Clock Wiring Clock Input SDRAMs *CK0/CK0 6 SDRAMs *CK1/CK1 6 SDRAMs *CK2/CK2 6 SDRAMs
* Wire per Clock Loading Table/ Wiring Diagrams
D8
D17 Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2
SDA
BA0-BA1 A0-A13 RAS CAS CKE0 CKE1 WE
BA0-BA1 : SDRAMs D0-D17 A0-A13 : SDRAMs D0-D17 RAS : SDRAMs D0-D17 CAS : SDRAMs D0-D17 CKE : SDRAMs D0-D8 CKE : SDRAMs D9-D17 WE : SDRAMs D0-D17
Notes : 1. 2. 3. 4.
DQ-to-I/O wring may be changed within a byte. DQ/DQS/DM/CKE/S relationships are maintained as shown. DQ/DQS/DM/DQS resistors are 22 Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ.
REV 2.2
Aug 3, 2004
8
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM Functional Block Diagram
1 Rank, 9 devices (ECC), 32Mx8 DDR SDRAMs
S0 DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DM8/DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 BA0-BA1 A0-A13 RAS CAS CKE0 WE DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS SCL DQS WP D8 VDDSPD VDD/VDDQ VREF VSS VDDID A0 SA0 A1 SA1 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS
DQS4 DM4/DQS13 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5/DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6/DQS15 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7/DQS16 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 Serial PD A2 SA2 SPD D0-D8 D0-D8 D0-D8 Strap: see Note 4 * Clock Wiring Clock Input SDRAMs *CK0/CK0 3 SDRAMs *CK1/CK1 3 SDRAMs *CK2/CK2 3 SDRAMs
* Wire per Clock Loading Table/ Wiring Diagrams
D0
DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
CS
DQS
D4
D1
DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
CS
DQS
D5
D2
DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
CS
DQS
D6
D3
DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
CS
DQS
D7
SDA
BA0-BA1 : SDRAMs D0-D8 A0-A13 : SDRAMs D0-D8 RAS : SDRAMs D0-D8 CAS : SDRAMs D0-D8 CKE : SDRAMs D0-D8 WE : SDRAMs D0-D8 Notes : 1. DQ-to-I/O wring may be changed within a byte. 2. DQ/DQS/DM/CKE/S relationships are maintained as shown. 3. DQ/DQS/DM/DQS resistors are 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ.
REV 2.2
Aug 3, 2004
9
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM Serial Presence Detect
SPD Description Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Description Number of Serial PD Bytes Written during Production Total Number of Bytes in Serial PD device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of DIMM Rank Data Width of Assembly Data Width of Assembly (cont') Voltage Interface Level of this Assembly DDR SDRAM Device Cycle Time CL=2.5 DDR SDRAM Device Access Time from Clock CL=2.5 DIMM Configuration Type Refresh Rate/Type Primary DDR SDRAM Width Error Checking DDR SDRAM Device Width DDR SDRAM Device Attr: Min CLK Delay, Random Col Access DDR SDRAM Device Attributes: Burst Length Supported DDR SDRAM Device Attributes: Number of Device Banks DDR SDRAM Device Attributes: CAS Latencies Supported DDR SDRAM Device Attributes: CS Latency DDR SDRAM Device Attributes: WE Latency DDR SDRAM Device Attributes: DDR SDRAM Device Attributes: General Byte 26 27 28 29 30 31 32 33 34 35 36-40 41 42 43 44 45 46-61 62 63 64-71 72 73-90 91-92 Description Maximum Data Access Time from Clock at CL=1 Minimum Row Precharge Time (tRP) Minimum Row Active to Row Active delay (tRRD) Minimum RAS to CAS delay (tRCD) Minimum RAS Pulse Width (tRAS) Module Bank Density Address and Command Setup Time Before Clock Address and Command Hold Time After Clock Data Input Setup Time Before Clock Data Input Hold Time After Clock Reserved Minimum Active/Auto-refresh Time (tRC) Auto-refresh to Active/Auto-refresh Command Period (tRFC) Max Cycle Time (tCK max) Maximum DQS-DQ Skew Time (tDQSQ) Maximum Read Data Hold Skew Factor (tQHS) Reserved SPD Revision Checksum Data Manufacturer's JEDEC ID Code Module Manufacturing Location Module Part number Module Revision Code Module Manufacturing Data 23 Minimum Clock Cycle CL=2.5 yy= Binary coded decimal year code, 0-99(Decimal), 93-94 00-63(Hex) ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex) 24 25 Maximum Data Access Time from Clock at CL=2 Minimum Clock Cycle Time at CL=1 95-98 99-127 Module Serial Number Reserved
REV 2.2
Aug 3, 2004
10
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM
SPD Values for NT512D64S8HBxGx
PC3200 (5T) Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-40 41 42 43 44 45 46-61 62 63 64-71 72 73-90 91-92 93-94 95-98 99-127 Value 128 256 SDRAM DDR 13 10 2 x64 x64 SSTL 2.5V 5.0ns 6.0ns Non-Parity SR/1x(7.8us) x8 N/A 1 Clock 2,4,8 4 2/2.5/3 0 1 Differential Clock 0.1V Tolerance 6ns 0.70ns 7.5ns 7.5ns 15ns 10ns 15ns 40ns 256MB 0.60ns 0.60ns 0.40ns 0.40ns Reserved 55ns 70ns 8ns 0.4ns 0.50ns Reserved Initial Checksum NANYA Assembly Module PN Revision Year/Week Code Serial Number Reserved Hex 80 08 07 0D 0A 02 40 00 04 50 60 00 82 08 00 01 0E 04 1C 01 02 20 00 60 70 75 75 3C 28 3C 28 40 60 60 40 40 00 37 46 20 28 50 00 00 8F 7F7F7F0B 00000000 ------Assembly Module PN Revision Year/Week Code Serial Number Reserved PC2700 (6K) Value 128 256 SDRAM DDR 13 10 2 x64 x64 SSTL 2.5V 6.0ns 7.0ns Non-Parity SR/1x(7.8us) x8 N/A 1 Clock 2,4,8 4 2/2.5 0 1 Differential Clock 0.2V Tolerance 7.5ns 0.70ns N/A N/A 18ns 12ns 18ns 42ns 256MB 0.75ns 0.75ns 0.45ns 0.45ns Reserved 60ns 72ns 12ns 0.4ns 0.55ns Reserved Initial Checksum NANYA Hex 80 08 07 0D 0A 02 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20 00 75 70 00 00 48 30 48 2A 40 75 75 45 45 00 3C 48 30 28 55 00 00 3C 7F7F7F0B 00000000 ------Assembly Module PN Revision Year/Week Code Serial Number Reserved PC2100 (75B) Value 128 256 SDRAM DDR 13 10 2 x64 x64 SSTL 2.5V 7.5ns 7.5ns Non-Parity SR/1x(7.8us) x8 N/A 1 Clock 2,4,8 4 2/2.5 0 1 Differential Clock 0.2V Tolerance 10ns 0.75ns N/A N/A 20ns 15ns 20ns 45ns 256MB 0.90ns 0.90ns 0.50ns 0.50ns Reserved 65ns 75ns 12ns 0.5ns 0.75ns Reserved Initial Checksum NANYA Hex 80 08 07 0D 0A 02 40 00 04 75 75 00 82 08 00 01 0E 04 0C 01 02 20 00 A0 75 00 00 50 3C 50 2D 40 90 90 50 50 00 41 4B 30 32 75 00 00 23 7F7F7F0B 00000000 -------
REV 2.2
Aug 3, 2004
11
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM
SPD Values for NT256D64S88BxGx
PC3200 (5T) Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-40 41 42 43 44 45 46-61 62 63 64-71 72 73-90 91-92 93-94 95-98 99-127 Value 128 256 SDRAM DDR 13 10 1 x64 x64 SSTL 2.5V 5.0ns 6.0ns Non-Parity SR/1x(7.8us) x8 N/A 1 Clock 2,4,8 4 2.5/3 0 1 Differential Clock 0.1V Tolerance 5ns 0.60ns N/A N/A 15ns 10ns 15ns 40ns 256MB 0.60ns 0.60ns 0.40ns 0.40ns Reserved 60ns 72ns 12ns 0.4ns 0.55ns Reserved Initial Checksum NANYA Assembly Module PN Revision Year/Week Code Serial Number Reserved Hex 80 08 07 0D 0A 01 40 00 04 50 60 00 82 08 00 01 0E 04 18 01 02 20 00 50 60 00 00 3C 28 3C 28 40 60 60 40 40 00 3C 48 30 28 55 00 00 9C 7F7F7F0B 00000000 ------Assembly Module PN Revision Year/Week Code Serial Number Reserved PC2700 (6K) Value 128 256 SDRAM DDR 13 10 1 x64 x64 SSTL 2.5V 6.0ns 7.0ns Non-Parity SR/1x(7.8us) x8 N/A 1 Clock 2,4,8 4 2/2.5 0 1 Differential Clock 0.2V Tolerance 7.5ns 0.70ns N/A N/A 18ns 12ns 18ns 42ns 256MB 0.75ns 0.75ns 0.45ns 0.45ns Reserved 60ns 72ns 12ns 0.4ns 0.55ns Reserved Initial Checksum NANYA Hex 80 08 07 0D 0A 01 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20 00 75 70 00 00 48 30 48 2A 40 75 75 45 45 00 3C 48 30 28 55 00 00 3B 7F7F7F0B 00000000 ------Assembly Module PN Revision Year/Week Code Serial Number Reserved PC2100 (75B) Value 128 256 SDRAM DDR 13 10 1 x64 x64 SSTL 2.5V 7.5ns 7.5ns Non-Parity SR/1x(7.8us) x8 N/A 1 Clock 2,4,8 4 2/2.5 0 1 Differential Clock 0.2V Tolerance 10ns 0.75ns N/A N/A 20ns 15ns 20ns 45ns 256MB 0.90ns 0.90ns 0.50ns 0.50ns Reserved 60ns 72ns 12ns 0.4ns 0.55ns Reserved Initial Checksum NANYA Hex 80 08 07 0D 0A 01 40 00 04 75 75 00 82 08 00 01 0E 04 0C 01 02 20 00 A0 75 00 00 50 3C 50 2D 40 90 90 50 50 00 3C 48 30 28 55 00 00 F0 7F7F7F0B 00000000 -------
REV 2.2
Aug 3, 2004
12
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM
SPD Values for NT128D64SH4B1G
PC3200 (5T) Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-40 41 42 43 44 45 46-61 62 63 64-71 72 73-90 91-92 93-94 95-98 99-127 Value 128 256 SDRAM DDR 13 9 1 x64 x64 SSTL 2.5V 5.0ns 6.0ns Non-Parity SR/1x(7.8us) x16 N/A 1 Clock 2,4,8 4 2.5/3 0 1 Differential Clock 0.1V Tolerance 5ns 0.60ns N/A N/A 15ns 10ns 15ns 40ns 128MB 0.60ns 0.60ns 0.40ns 0.40ns Reserved 60ns 72ns 12ns 0.4ns 0.55ns Reserved Initial Checksum NANYA Assembly Module PN Revision Year/Week Code Serial Number Reserved Hex 80 08 07 0D 09 01 40 00 04 50 60 00 82 10 00 01 0E 04 18 01 02 20 00 50 60 00 00 3C 28 3C 28 20 60 60 40 40 00 3C 48 30 28 55 00 00 83 7F7F7F0B 00000000 ------Assembly Module PN Revision Year/Week Code Serial Number Reserved PC2700 (6K) Value 128 256 SDRAM DDR 13 9 1 x64 x64 SSTL 2.5V 6.0ns 7.0ns Non-Parity SR/1x(7.8us) x16 N/A 1 Clock 2,4,8 4 2/2.5 0 1 Differential Clock 0.2V Tolerance 7.5ns 0.70ns N/A N/A 18ns 12ns 18ns 42ns 128MB 0.75ns 0.75ns 0.45ns 0.45ns Reserved 60ns 72ns 12ns 0.4ns 0.55ns Reserved Initial Checksum NANYA Hex 80 08 07 0D 09 01 40 00 04 60 70 00 82 10 00 01 0E 04 0C 01 02 20 00 75 70 00 00 48 30 48 2A 20 75 75 45 45 00 3C 48 30 28 55 00 00 22 7F7F7F0B 00000000 ------Assembly Module PN Revision Year/Week Code Serial Number Reserved PC2100 (75B) Value 128 256 SDRAM DDR 13 9 1 x64 x64 SSTL 2.5V 7.5ns 7.5ns Non-Parity SR/1x(7.8us) x16 N/A 1 Clock 2,4,8 4 2/2.5 0 1 Differential Clock 0.2V Tolerance 10ns 0.75ns N/A N/A 20ns 15ns 20ns 45ns 128MB 0.90ns 0.90ns 0.50ns 0.50ns Reserved 60ns 72ns 12ns 0.4ns 0.55ns Reserved Initial Checksum NANYA Hex 80 08 07 0D 09 01 40 00 04 75 75 00 82 10 00 01 0E 04 0C 01 02 20 00 A0 75 00 00 50 3C 50 2D 20 90 90 50 50 00 3C 48 30 28 55 00 00 D7 7F7F7F0B 00000000 -------
REV 2.2
Aug 3, 2004
13
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM
SPD Values for NT512D72S8PB0G
PC3200 (5T) Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-40 41 42 43 44 45 46-61 62 63 64-71 72 73-90 91-92 93-94 95-98 99-127 Value 128 256 SDRAM DDR 13 10 2 x74 x74 SSTL 2.5V 5.0ns 6.0ns Parity SR/1x(7.8us) x8 ECC Width 1 Clock 2,4,8 4 2.5/3 0 1 Differential Clock 0.1V Tolerance 5ns 0.60ns N/A N/A 15ns 10ns 15ns 40ns 256MB 0.60ns 0.60ns 0.40ns 0.40ns Reserved 60ns 72ns 12ns 0.4ns 0.55ns Reserved Initial Checksum NANYA Assembly Module PN Revision Year/Week Code Serial Number Reserved Hex 80 08 07 0D 0A 02 48 00 04 50 60 02 82 08 08 01 0E 04 18 01 02 20 00 50 60 00 00 3C 28 3C 28 40 60 60 40 40 00 3C 48 30 28 55 00 00 AF 7F7F7F0B 00000000 -------
REV 2.2
Aug 3, 2004
14
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM
SPD Values for NT256D72S89B0G
PC3200 (5T) Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-40 41 42 43 44 45 46-61 62 63 64-71 72 73-90 91-92 93-94 95-98 99-127 Value 128 256 SDRAM DDR 13 10 1 x72 x72 SSTL 2.5V 5.0ns 6.0ns Parity SR/1x(7.8us) x8 ECC Width 1 Clock 2,4,8 4 2.5/3 0 1 Differential Clock 0.1V Tolerance 5ns 0.60ns N/A N/A 15ns 10ns 15ns 40ns 256MB 0.60ns 0.60ns 0.40ns 0.40ns Reserved 60ns 72ns 12ns 0.4ns 0.55ns Reserved Initial Checksum NANYA Assembly Module PN Revision Year/Week Code Serial Number Reserved Hex 80 08 07 0D 0A 01 48 00 04 50 60 02 82 08 08 01 0E 04 18 01 02 20 00 50 60 00 00 3C 28 3C 28 40 60 60 40 40 00 3C 48 30 28 55 00 00 AE 7F7F7F0B 00000000 -------
REV 2.2
Aug 3, 2004
15
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM Absolute Maximum Ratings
Symbol VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT Parameter Voltage on I/O pins relative to VSS Voltage on Input relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating Temperature (Ambient) Storage Temperature (Plastic) Power Dissipation (per device component) Short Circuit Output Current Rating -0.5 to VDDQ +0.5 -0.5 to +3.6 -0.5 to +3.6 -0.5 to +3.6 0 to +70 -55 to +150 1 50 Units V V V V C C W mA
Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics and Operating Conditions
TA= 0C ~ 70C; VDDQ= VDD= 2.5V0.2V(PC2100,PC2700); TA= 0C ~ 70C; VDDQ= VDD= 2.6V0.1V(PC3200) Symbol VDD Supply Voltage Parameter PC2100, PC2700 PC3200 VDDQ VSS, VSSQ VREF VTT VIH (DC) VIL (DC) VIN (DC) VID (DC) I/O Supply Voltage PC2100, PC2700 PC3200 Supply Voltage, I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (System) Input High (Logic1) Voltage Input Low (Logic0) Voltage Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs Input Leakage Current II Any input 0V VIN VDD; All other pins not under test = 0V Output Leakage Current IOZ DQs are disabled; 0V Vout VDDQ Output High Current IOH (VOUT = VDDQ -0.373V, min VREF, min VTT) Output Low Current IOL (VOUT = 0.373, max VREF, max VTT) 16.8 mA 1 -16.8 mA 1 -10 10 -10 10 A 1 Min 2.3 2.7 2.5 2.3 2.7 2.5 0 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.30 0 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 V V V V V V V 1, 2 1, 3 1 1 1 1, 4 V 1 V 1 Max Units Notes
A
1
1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK.
REV 2.2
Aug 3, 2004
16
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM AC Characteristics
Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified. 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level.
AC Output Load Circuits
VTT 50 ohms Output VOUT 30 pF Timing Reference Point
AC Operating Conditions
TA = 0 C ~ 70 C; VDDQ= VDD= 2.5V 0.2V (PC2100/PC2700); VDDQ= VDD= 2.6V 0.1V (PC3200) Symbol VIH (AC) VIL (AC) VID (AC) VIX (AC) Parameter/Condition Input High (Logic 1) Voltage. Input Low (Logic 0) Voltage. Input Differential Voltage, CK and CK Inputs Input Differential Pair Cross Point Voltage, CK and CK Inputs 0.62 (0.5* VDDQ) - 0.2 Min VREF + 0.31 VREF - 0.31 VDDQ + 0.6 (0.5* VDDQ) + 0.2 Max Unit V V V V Notes 1, 2 1, 2 1, 2, 3 1, 2, 4
1. Input slew rate = 1V/ ns. 2. Inputs are not recognized as valid until VREF stabilizes. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
REV 2.2
Aug 3, 2004
17
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM Operating, Standby, and Refresh Currents
TA = 0 C ~ 70 C; VDDQ= VDD= 2.5V 0.2V (PC2100/PC2700); VDDQ= VDD= 2.6V 0.1V (PC3200) Symbol IDD0 IDD1 IDD2P IDD2N IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 Parameter/Condition Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) Auto-Refresh Current: tRC = tRFC (MIN) Self-Refresh Current: CKE 0.2V Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. Notes 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2,3 1,2 1,2
1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate = 1V/ ns. 3. Current at 7.8 s is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 s. All IDD current values are calculated from device level.
REV 2.2
Aug 3, 2004
18
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM
NT512D64S8HB1Gx Symbol PC3200 (5T) IDD0 IDD1 IDD2P IDD2N IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 1915 1995 340 765 357 1275 3275 3195 3675 51 5275 PC2700 (6K) 1755 1995 340 765 357 1275 3275 3195 2875 51 5275 PC2100 (75B) 1585 1825 340 680 306 1105 2705 2625 2785 51 4065
NT256D64S88B1Gx PC3200 (5T) 995 1035 180 405 189 675 1675 1635 1875 27 2675 PC2700 (6K) 915 1035 180 405 189 675 1675 1635 1475 27 2675 PC2100 (75B) 825 945 180 360 162 585 1385 1345 1425 27 2065
NT128D64SH4B1G PC3200 (5T) 460 480 80 180 84 300 800 780 900 12 1300 PC2700 (6K) 420 480 80 180 84 300 800 780 700 12 1300 PC2100 (75B) 380 440 80 160 72 260 660 640 680 12 1000
NT512D72S8PB0G Symbol PC3200 (5T) IDD0 IDD1 IDD2P IDD2N IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 1915 1995 340 765 357 1275 3275 3195 3675 51 5275 PC2700 (6K) 1755 1995 340 765 357 1275 3275 3195 2875 51 5275 PC2100 (75B) 1585 1825 340 680 306 1105 2705 2625 2785 51 4065
NT256256D64S89B0G PC3200 (5T) 995 1035 180 405 189 675 1675 1635 1875 27 2675 PC2700 (6K) 915 1035 180 405 189 675 1675 1635 1475 27 2675 PC2100 (75B) 825 945 180 360 162 585 1385 1345 1425 27 2065
REV 2.2
Aug 3, 2004
19
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module
TA = 0 C ~ 70 C; VDDQ= VDD= 2.5V 0.2V (PC2100/PC2700); VDDQ= VDD= 2.6V 0.1V (PC3200) (Part 1 of 2) Symbol Parameter 5T PC3200 Min. tAC tDQSCK tCH tCL tCK tCK tCK tDH DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock cycle time CL=3 Clock cycle time CL=2.5 Clock cycle time CL=2 DQ and DM input hold time -0.65 -0.55 0.45 0.45 5 6 0.4 Max. +0.65 +0.55 0.55 0.55 8 12 Min. -0.7 -0.7 0.45 0.45 6 7.5 0.45 6K PC2700 Max. +0.7 +0.7 0.55 0.55 12 12 Min. -0.75 -0.75 0.45 0.45 7.5 10 0.5 75B PC2100 Max. +0.75 +0.75 0.55 0.55 12 12 ns ns ns 1-4 1-4 1-4, 15, 16 1-4, 15, 16 1-4 1-4, 5 ns ns tCK tCK 1-4 1-4 1-4 1-4 Unit Notes
tDS tDIPW tHZ
DQ and DM input setup time DQ and DM input pulse width (each input) Data-out high-impedance time from CK/CK
0.4 1.75 -0.6 +0.6
0.45 1.75 -0.7 +0.7
0.5 1.75 -0.75 +0.75
ns ns ns
tLZ tDQSQ tHP tQH tQHS tDQSS tDQSL, tDQSH tDSS tDSH tMRD tWPRES tWPST tWPRE tIH
Data-out low-impedance time from CK/CK DQS-DQ skew (DQS & associated DQ signals) Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time Data output hold time from DQS Data hold Skew Factor Write command to 1st DQS latching transition DQS input low (high) pulse width (write cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate)
-0.6
+0.6 0.4
-0.7
+0.7 0.45
-0.75
+0.75 0.5
ns ns tCK tCK
1-4, 5 1-4 1-4
tCH or tCL tHP tQHS 0.5 0.75 0.35 0.2 0.2 2 0 0.40 0.25 0.6 0.60 1.25
tCH or tCL tHP tQHS 0.55 0.75 0.35 0.2 0.2 2 0 0.40 0.25 0.75 0.60 1.25
tCH or tCL tHP tQHS 0.75 0.75 0.35 0.2 0.2 2 0 0.40 0.25 0.9 0.60 1.25
1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4, 7 1-4, 6 1-4 2-4, 9, 11, 12 2-4, 9, 11, 12 2-4,
ns tCK tCK tCK tCK tCK ns tCK tCK ns
tIS
0.6
0.75
0.9
ns
tIH
0.7
0.8
1.0
ns
10, 11, 12, 14
REV 2.2
Aug 3, 2004
20
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module
TA = 0 C ~ 70 C; VDDQ= VDD= 2.5V 0.2V (PC2100/PC2700); VDDQ= VDD= 2.6V 0.1V (PC3200) (Part 2 of 2) 5T Symbol Parameter PC3200 Min. Address and control input setup time tIS tIPW tRP RE tRP ST tRAS tRC tRFC tRCD tRAP tRP tRRD tWR tDAL tWTR tPDEX tXSNR tXSRD tREFI 0.7 (slow slew rate) Input pulse width Read preamble Read postamble Active to Precharge command Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command 70 period Active to Read or Write delay Active to Read Command with Auto-precharge Precharge command period Active bank A to Active bank B command Write recovery time Auto-precharge write recovery + precharge time Internal write to read command delay Power down exit time Exit self-refresh to non-read command Exit self-refresh to read command Average Periodic Refresh Interval 15 15 15 10 15 (tWR/ tCK ) + (tRP / tCK ) 1 5 75 200 7.8 18 18 18 12 15 (tWR/ tCK ) + (tRP / tCK ) 1 6 75 200 7.8 20 20 20 15 15 (tWR/ tCK ) + (tRP / tCK ) 1 7.5 75 200 7.8 ns ns ns ns ns tCK tCK ns ns tCK s 1-4 1-4 1-4 1-4 1-4 1-4, 13 1-4 1-4 1-4 1-4 1-4, 8 72 75 2.2 0.9 0.40 42ns 55 1.1 0.60 120us 2.2 0.9 0.40 42ns 60 1.1 0.60 120us 2.2 0.9 0.40 45ns 65 1.1 0.60 120us ns ns ns tCK tCK 0.8 1.0 ns Max. Min. 6K PC2700 Max. Min. 75B PC2100 Max. 2-4, 10-12, 14 2-4, 12 1-4 1-4 1-4 1-4 1-4 Unit Notes
REV 2.2
Aug 3, 2004
21
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM AC Timing Specification Notes
1. Input slew rate = 1V/ns. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this time, depending on tDQSS. 8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device. 9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 11. CK/CK slew rates are >= 1.0 V/ns. 12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. For example, for PC2100 at CL= 2.5, tDAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5. 14. An input setup and hold time derating table is used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns. Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns 1. 2. Delta (tIS) 0 +50 +100 Delta (tIH) 0 0 0 Unit ps ps ps Note 1, 2 1, 2 1, 2
Input slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising transitions. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
15. An input setup and hold time derating table is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns 1. 2. Delta (tDS) 0 +75 +150 Delta (tDH) 0 +75 +150 Unit ps ps ps Note 1, 2 1, 2 1, 2
I/O slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising transitions. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
16. An I/O Delta Rise, Fall Derating table is used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ. Delta Rise and Fall Rate 0.0 ns/V 0.25 ns/V 0.5 ns/V 1. 2. 3. Delta (tDS) 0 +50 +100 Delta (tDH) 0 +50 +100 Unit ps ps ps Note 1-4 1-4 1-4
4.
Input slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising transitions. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V Using the table above, this would result in an increase in tDS and tDH of 100 ps. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
REV 2.2
Aug 3, 2004
22
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM Package Dimensions
Non-ECC, 16 TSOP devices
FRONT
133.35 5.250 128.93 5.076 (2x)4.00 0.157
10.0 0.394
0.098
Detail A
Detail B
2.30 0.91
2.50
BACK
4.00 0.157 MAX
Detail A 3.80 0.150 4.00 0.157
Detail B 1.00 Width 0.039
1.27+/- 0.10 0.050 +/- 0.004
6.35 0.250 1.80 0.071
1.27 Pitch 0.05
Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches)
REV 2.2
Aug 3, 2004
23
NANYA reserves the right to change products and specifications without notice.
Preliminary
17.80 0.700
Side
(c) NANYA TECHNOLOGY CORPORATION
31.75 1.250
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM Package Dimensions
Non-ECC, 8 TSOP devices
FRONT
133.35 5.250 128.93 5.076 (2x)4.00 0.157
10.0 0.394
0.098
Detail A
Detail B
2.30 0.91
2.50
BACK
3.18 0.125 MAX
Detail A 3.80 0.150 4.00 0.157
Detail B 1.00 Width 0.039
1.27+/- 0.10 0.050 +/- 0.004
6.35 0.250 1.80 0.071
1.27 Pitch 0.05
Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches)
REV 2.2
Aug 3, 2004
24
NANYA reserves the right to change products and specifications without notice.
Preliminary
17.80 0.700
Side
(c) NANYA TECHNOLOGY CORPORATION
31.75 1.250
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM Package Dimensions
Non-ECC, 4 TSOP devices
FRONT
133.35 5.250 128.93 5.076 (2x)4.00 0.157
10.00 0.394
0.098
Detail A
Detail B
2.30 0.91
2.50
BACK
3.18 0.125 MAX
Detail A 3.80 0.150 4.00 0.157
Detail B 1.00 Width 0.039
1.27+/- 0.10 0.050 +/- 0.004
6.35 0.250 1.80 0.071
1.27 Pitch 0.05
Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches)
REV 2.2
Aug 3, 2004
25
NANYA reserves the right to change products and specifications without notice.
Preliminary
17.80 0.700
Side
(c) NANYA TECHNOLOGY CORPORATION
31.75 1.250
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM Package Dimensions
ECC, 18 TSOP devices
FRONT
133.35 5.25 128.95 5.077 (2x)4.00 0.157
10.0 0.394
(2) 2.50 0.098
Detail A
Detail B
2.30 0.091
BACK
4.00 0.157 max.
Detail A 3.80 0.150 4.00 0.157
Detail B 1.00 Width 0.039
1.27+/- 0.10 0.050 +/- 0.004
6.35 0.250 1.80 0.071
1.27 Pitch 0.05
Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches)
REV 2.2
Aug 3, 2004
26
NANYA reserves the right to change products and specifications without notice.
Preliminary
17.80 0.700
Side
(c) NANYA TECHNOLOGY CORPORATION
31.75 1.250
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM Package Dimensions
ECC, 9 TSOP devices
FRONT
133.35 5.25 128.95 5.077 (2x)4.00 0.157
10.0 0.394
(2) 2.50 0.098
Detail A
Detail B
2.30 0.091
BACK
2.59 0.157 max.
Detail A 3.80 0.150 4.00 0.157
Detail B 1.00 Width 0.039
1.27+/- 0.10 0.050 +/- 0.004
6.35 0.250 1.80 0.071
1.27 Pitch 0.05
Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches)
REV 2.2
Aug 3, 2004
27
NANYA reserves the right to change products and specifications without notice.
Preliminary
17.80 0.700
Side
(c) NANYA TECHNOLOGY CORPORATION
31.75 1.250
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC) Unbuffered DDR DIMM Revision Log
Rev 0.1 1.0 Date 12/2003 Dec 19,2003 Updated format. Release Correction to block diagram label. 1.1 Feb 11, 2004 Correction to SPD bank and checksum values. Package dimension added for x8 wide devices. Document reorganized by order of B die generation / size and DIMM format. DIMM: unbuffered DIMM Speed grades: 5T, 6K, 75B 2.0 Mar 4, 2004 Modules: NT512D64S8HB1G, NT256D64S88B1G, NT128D64SH4B1G Modules: NT512D72S8PB0G, NT256D72S89B0G Modules: NT512D64S8HB1GY, NT256D64S88B1GY 2.1 2.2 May 11, 2004 Aug 3, 2004 Added NT256D64S88B0G-6K speed grade to ordering information. Corrected SPD contents. Modification
Nanya Technology Corporation
Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688
Please visit our home page for more information: www.nanya.com
Nanya reserves the right to make changes or deletions without any notice to any of its products. Nanya makes no guarantee, warranty or representation regarding the suitability of its products for any particular purpose. Nanya assumes no liability arising out of the application or use of its products. All parameters can and do vary in its application and must be validated for each customer application by the customer's technician. By purchasing Nanya products, Nanya does not convey any license under its patent rights not the rights of others. Nanya products are not designed or intended or authorized for use in systems intended for the military or surgical implants or any other applications where life is involved or where injury or death may occur or the loss/corruption of data or the loss of system reliability or mission critical applications. Should the buyer purchase or use Nanya products in such unintended or unauthorized application, the Buyer and user shall indemnify and hold Nanya and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, costs, damages, all fees and expenses directly or indirectly arising from any claim of loss, injury or death associated with unintended or unauthorized use even if such claims alleges Nanya was negligent regarding design or manufacture of the part. Nanya and the Nanya logo are trademarks of the Nanya Technology Corporation.
Printed in Taiwan (c)2004
REV 2.2
Aug 3, 2004
28
NANYA reserves the right to change products and specifications without notice.
(c) NANYA TECHNOLOGY CORPORATION
Preliminary

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